The present disclosure relates to semiconductor devices, such as high voltage MOS (metal oxide semiconductor) FETs (field effect transistors), and methods for fabricating the same.
In recent years, as the number of elements integrated into a single semiconductor integrated circuit device has been increased, semiconductor integrated circuit devices have been required to integrate high voltage MOS devices, low voltage CMOS (complementary metal oxide semiconductor) devices, bipolar devices, and the like on a single substrate. Characteristics required for high voltage MOS devices include high breakdown voltage, and, in view of shrinking chips, reducing costs, etc., low on-resistance.
Conventionally, high voltage MOS transistors employ a technique for increasing static breakdown voltage (drain breakdown voltage when the gate is in the “off” condition) by forming an electric-field limiting layer in a drain region. However, an electric-field limiting layer formed in a drain region acts as a resistive component during operation of the transistor, causing an increase in on-resistance per unit area of the device. In this way, there is a trade-off between static breakdown voltage and on-resistance.
As one of the techniques for improving such a trade-off between static breakdown voltage and on-resistance, a method is disclosed in which, e.g., in a conventional high voltage MOS transistor, a source region is formed in the surface of a body layer in a self-aligned manner with respect to a sidewall spacer to effectively suppress “surface punch-through” and increase breakdown voltage and current carrying capacity (see Japanese Laid-Open Publication No. 7-176640, for example).
Characteristics of a conventional high voltage MOS transistor will be described below with reference to FIG. 7. As shown in FIG. 7, a P-well 4 and an N-well 5 are formed spaced away from each other in surface portions of an N-type epitaxial layer 3 formed in an upper part of a P-type semiconductor substrate 1. An N+-type buried layer 2 is formed between the P-type semiconductor substrate 1 and the N-type epitaxial layer 3 to suppress operation of a parasitic transistor formed by the P-well 4, the N-type epitaxial layer 3, and the P-type semiconductor substrate 1.
A gate electrode 12 is formed over the P-well 4 with a gate insulating film 11 interposed therebetween. With this gate electrode 12 used as a mask, a P-type base region (channel diffusion region) 7 is formed in a surface portion of the P-well 4 in a self-aligned manner. The P-type base region 7 has a greater diffusion depth than a channel ion bombardment layer 6 underlying the gate electrode 12. The gate electrode 12 extends out over the N-well 5, and a local oxidation film 17 is formed between the extended part of the gate electrode 12 and the P-type semiconductor substrate 1.
An insulating sidewall spacer 10 of an oxide film or the like is formed on the sides of the gate electrode 12 by a CVD (chemical vapor deposition) process. By double diffusion using this insulating sidewall spacer 10 and the gate electrode 12 as a mask, an N+-type source region 8 is formed in the P-type base region 7 in a self-aligned manner, and an N+-type well contact (drain) region 9 is formed in the N-well 5.
An interlayer dielectric film 16 is formed on the P-type semiconductor substrate 1 as well as over the gate electrode 12, and contact plugs 13 and 14, which are respectively coupled to the N+-type well contact region 9 and the N+-type source region 8, are formed in contact holes made in the interlayer dielectric film 16. On the interlayer dielectric film 16, extraction electrodes 15 are formed, which are coupled to the respective contact plugs 13 and 14 and serve as a source electrode and a drain electrode. A passivation film (not shown) is formed on the interlayer dielectric film 16 as well as on the extraction electrodes 15.
The conventional example set forth above is characterized in that the N+-type source region 8 is formed in a self-aligned manner by double diffusion using the insulating sidewall spacer 10 and the gate electrode 12 as a mask, rather than only using the gate electrode 12 as a mask, thereby increasing the size of the channel region formed of the P-type base region 7 in a lateral direction by the width of the insulating sidewall spacer 10. This provides effective suppression of “surface punch-through”, thereby increasing both breakdown voltage and current carrying capacity.